Starting date : Jun. 2018 > May 2021Lifetime: 36 months
Program in support : ECSEL Research and Innovation Actions (RIA)
Status project : in progress
CEA-Leti's contact :
Arnaud Garnier
Yves Quéré
Project Coordinator: UMS (FR)
Partners: - Airbus-Tesat, (DE)
- Fraunhofer IAF, (DE)
- UMS GmbH, (DE)
- University of Erlangen, (DE)
- X-Fab Dresden, (DE)
- III-V Lab, (FR)
- CEA-Leti, (FR)
- Thales Communications et Security, (FR)
- UMS France, (FR)
- Benetel, University College Dublin, (IE)
- MEC, University of Padova, (IT)
- Molecular Plasma Group, (LU)
- Sencio, (NL)
- Ericsson A, (SE)
- SweGaN AB, (SE)
- Slovak University of Technology in Bratislava, (SK)
Target market: n/a
Investment: € 21.4 m.
EC Contribution: € 6 m.
| Stakes
The first project contribution involves demonstration of CMOS-compatible 200 mm GaN on Si epitaxy and subsequent Ka band (26.5 to 40 GHz) transistor processing: • Epitaxy: GaN epitaxy on HR (High Resistivity) silicon substrates has been fine-tuned to reduce RF losses from 2.5 db/mm to 0.8 dB/mm. This is sufficient for current transistor integration work, but further improvement (<0.4 dB/mm) is required to demonstrate high performance transistors • Ohmic contact brick: high performance, innovative and CMOS-compatible, ion-implanted ohmic contacts have been demonstrated (0.06 Ohm.mm) • Transistor: transistor and test structure have been designed and corresponding mask set ERIS, combining optical and e-beam lithography, has been completed. CMOS compatible Ka-band transistor process flow has been defined (Au-free, lift-off free). The second project contribution involves a System in Package (SiP) solution for mm wave devices: • Advanced packaging solutions: fan-out wafer level packaging (FOWLP) in chip first face down configuration has been selected for 5G base transceiver station (BTS) applications. This solution includes an innovative molding opening for thermal dissipation • Thermal simulation for material and design optimization • SiP design of the first demonstrator dedicated to 5G BTS @26-28 GHz • SiP building block development: use of CEA-Leti’s 200 mm clean room facility for the FOWLP solution and a subcontractor for molding compound removal by laser • Moisture protection barrier layer at wafer level: work is ongoing to select the best coating material for withstanding 85°C / 85% RH for 1000h under bias • Design and simulation of highly linear 45nm RF SOI T/R switch for 39-GHz FEM SiP: RF simulated performance of the switch approaches performance found in silicon state of the art with ~2 dB insertion loss, ~20 dB isolation and adequate matching in both TX and RX modes. The IP1dB is +32.5 dBm.
A new generation of communication infrastructures is currently being developed. Fifth generation (5G) communications technologies will provide internet access to a wide range of applications spanneing billions of low data rate sensors to high resolution video streaming. The 5G network is designed to scale across these different use cases and is expected to use different radio access technologies for each use case.
To support very high data rates, 5G is projected to use wide bandwidth spectrum allocation at mm-wave frequencies. The bandwidth provided at mm-wave frequencies (above 24 GHz) is more than 10 times as broad as that in the lower bands (sub 6 GHz). However, the move to mm-waves comes with a drawback, specifically increased path loss. This makes it extremely challenging to provide coverage at mm-wave frequencies.
A partial remedy is to use beamforming to direct radio energy to a specific user. In some deployment scenarios, beamforming is insufficient and output power must also be increased. A major challenge is to bring affordable, high-performance mm-wave active antenna arrays into production. At present, there is market demand for these systems but there is still a capability gap.
The main objectives of the “5G_GaN2” project are to lower substantially cost and power consumption and to increase the output power of mm-wave active antenna systems. Advanced Gallium Nitride (GaN) technology has been retianed to achieve maximum output power and energy efficiency. High-volume, low-cost packaging and integration techniques developed for digital applications are being considered to achieve the cost and integration targets.
A number of application-driven demonstrators are planned for highlighting the capabilities of the developed technology. Their role is to guide the technology development towards maximum impact and take-up in the post-design phase. The consortium embraces the complete value chain including wafer suppliers, semiconductor fabrication and system integrators. Key universities and research institutes are guaranteeing academic excellence throughout the project.
IMPACT
Development of CMOS compatible technology on GaN/Si substrates will facilitate transfer to partner XFAB (GaN device foundry). Ion-implanted Ohmic contact is a promising alternative to the more complex technique used by the majority of stakeholders in this field.
FOWLP technology, including a thermal management solution, will allow development of low-cost, high-performance FEM components, circuit and SiPs for mm waves, 5G and SatCom applications in the 28 GHz, 39 GHz and 80 GHz range of frequencies.
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